1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method of the same, and in particular, to a dynamic random access memory (DRAM) and a manufacturing method of the same.
2. Description of the Background Art
Owing to remarkable spread of information equipments such as computers, demand for semiconductor memory devices has been rapidly increased. In particular, semiconductor devices having such functional features that they have large-scale memory capacities and are capable of high-speed operations have been demanded. Correspondingly, technical development has been progressed for high integration, high-speed responsibility and high reliability of the semiconductor memory devices.
Among the semiconductor memory devices, a DRAM (dynamic random access memory) has been known as a device capable of random input and output of memory information. In general, the DRAM is formed of a memory cell array, which is a memory region storing a large amount of memory information, and a peripheral circuit required for external input and output.
FIG. 58 is a block diagram showing a structure of a conventional DRAM. Referring to FIG. 58, a DRAM 150 includes a memory cell array 151 for storing data signals of memory information, a row and column address buffer 152 for externally receiving an address signal which is used for selecting the memory cell forming a unit memory circuit, row and column decoders 153 and 154 which decode the address signal to designate the memory cell, a sense refresh amplifier 155 which amplifies the signal stored in the designated memory cell to read the same, data-in and data-out buffers 156 and 157 for data input and data output, and a clock generator 158 for generating a clock signal.
The memory cell array 151 occupying a large area in the semiconductor chip is formed of a plurality of memory cells for storing unit memory information disposed in a matrix form. FIG. 59 is an equivalent circuit diagram showing memory cells for 4 bits forming the memory cell array 151. Each memory cell is formed of one MOS transistor and one capacitor connected thereto. Such memory cell is referred to as a memory cell of one-transistor and one-capacitor type. The memory cells of this type have simple structures and the degree of integration of the memory cell array can be easily increased, so that they have been widely used in DRAMs of large capacities.
The memory cells of the DRAMs can be classified into several types based on their structures of the capacitors. Among several types of the capacitors, a stacked type capacitor has such a feature that a major part of the capacitor may be extended over a gate electrode and a field isolating film, so that areas of opposed surfaces of electrodes of the capacitor can be increased and thus the capacitor capacity can be increased. Since the stacked type capacitor has the foregoing feature, a sufficient capacitor capacity can be ensured even if elements are miniaturized to a higher extent in accordance with the high integration of the semiconductor device. As a result, stacked type capacitors have been widely used in accordance with the high integration of the semiconductor devices. The semiconductor devices are now being integrated to a further extent, and the stacked type capacitors complying with it are now being developed. More specifically, there has been proposed a stacked type capacitor of a cylindrical form, which is intended to ensure an appropriate capacitor capacity even if the semiconductor device is further integrated and thus has further miniaturized elements.
FIG. 60 is a plan showing a DRAM provided with cylindrical stacked type capacitors which have been proposed. FIG. 61 is a cross section of the DRAM taken along line X--X in FIG. 60.
Referring to FIGS. 60 and 61, the proposed DRAM in the prior art includes a silicon substrate 201, an element isolating oxide film 202 formed on a predetermined region of a major surface of the silicon substrate 201 for isolating elements, source/drain regions 206a, 206b, 206c and 206d, which are formed in regions surrounded by the element isolating oxide film 202 with predetermined spaces therebetween and are located at opposite sides of channel regions 220, gate electrodes 204b and 204c formed on the channel regions 220 with gate oxide films 205 therebetween, word lines (gate electrodes) 204d and 204e formed on the element isolating oxide film 202 with a predetermined space therebetween, and insulating films 207 covering the gate electrodes 204b, 204c, 204d and 204e. The source/drain regions 206a and 206b and the gate electrode 204c form a transfer gate transistor 203 of one of the memory cells. The source/drain regions 206a and 206c and the gate electrode 204b form the transfer gate transistor 203 of the other memory cell.
The proposed DRAM in the prior art further includes a buried bit line 208 electrically connected to the source/drain region 206a, an insulating film 209 covering the buried bit line 208, base portions 211a forming storage nodes (capacitor lower electrodes) 211 which are electrically connected to the source/drain region 206b and extend over the insulating films 207 and 209, standing wall portions 211b which are located along outer peripheries of the base portions 211a and extend nearly perpendicularly (at an angle between 87 and 90 degrees) to the silicon substrate 201 for forming the storage nodes 211, a capacitor insulating film 212 covering the base portions 211a and the standing wall portions 211b, a cell plate 213 (capacitor upper electrode) covering the capacitor insulating film 212, an interlayer insulating film 214 covering the cell plate 213 and having a flat surface, interconnection layers 215 formed on the interlayer insulating film 214 and corresponding to the gate electrodes 204b, 204c, 204d and 204e, respectively, and a protection film 216 covering the interconnection layers 215. The base portion 211a and standing wall portion 211b, which form the storage node 211, as well as the capacitor insulating film 212 and the cell plate 213 form a cylindrical stacked type capacitor 210 for accumulating the charges corresponding to the data signal. The base portion 211a and the standing wall portion 211b, which form the storage node 211, are formed of polysilicon layers. The capacitor insulating film 212 is formed, e.g., of a nitride film. The cell plate 213 is formed of a polysilicon layer.
FIGS. 62-75 are cross sections showing a manufacturing process of the DRAM shown in FIG. 61. Referring to FIGS. 61 and 62-75, the manufacturing process of the conventional DRAM will be described below.
First, as shown in FIG. 62, the element isolating oxide film 202 is formed on the predetermined region of the major surface of the silicon substrate 1 by an LOCOS method.
Then, as shown in FIG. 63, a thermal oxidation method is used to form the gate oxide films 205, and then the gate electrodes (word lines) 204b, 204c, 204d and 204e are selectively formed. The insulating films 207 covering the gate electrodes 204b-204e are formed by two oxide film forming steps and two etching steps. The gate electrodes 204b, 204c, 204d and 204e covered with the insulating films 207 are used as a mask for an ion implantation, by which impurity is ion-implanted into the surface of the silicon substrate 201. Thereby, the source/drain regions 206a, 206b, 206c and 206d are formed.
Then, as shown in FIG. 64, a layer of a metal having high-melting point, e.g., of tungsten, molybdenum or titanium is formed and then is patterned into a predetermined shape. Thereby, the buried bit line 208 directly connected to the source/drain region 206a is formed. The insulating film 209 covering the buried bit line 208 is formed.
As shown in FIG. 65, a CVD method is used to form a polysilicon layer 211c doped with impurity on the whole surface of the silicon substrate 201. Then, as shown in FIG. 66, an insulating layer 235 of, e.g., silicon oxide film (SiO.sub.2) is formed. The thickness of this insulating layer 235 determines a height of the standing wall portion 211b which forms the storage node (the lower electrode of the capacitor).
As shown in FIG. 67, resist (not shown) is applied to the surface of the insulating layer 235, and lithography is used to pattern the same into a predetermined shape. Thereby, a resist pattern (capacitor insulating layer) 236 is formed. A width of the resist pattern 236 determines a space separating the adjacent capacitors.
As shown in FIG. 68, the resist pattern 236 is used as a mask for applying anisotropic etching, by which the insulating layer 235 is selectively removed. Thereafter, the resist pattern 236 is removed. Then, as shown in FIG. 69, an anisotropic etching is applied to the base portions 211a of the capacitor lower electrodes (storage node), using the insulating layer 235 as a mask.
A shown in FIG. 70, the CVD method is used to form a polysilicon layer 211d containing a large amount of doped arsenic or phosphorus at a thickness between 500 .ANG. and 1000 .ANG..
Then, as shown in FIG. 71, a reactive ion etching (RIE) method is used to apply anisotropic etching to the polysilicon layer 211d, whereby the standing wall portion 211b of the capacitor lower electrode (storage node) is formed. The conditions for carrying out the RIE are as follows. An RIE apparatus of a parallel flat plate type is used. A frequency is 13.56 MHz, an RF power is 0.3 KW/cm.sup.2, a gas pressure is 150 mTorr, a flow rate of Cl.sub.2 gas is 50 sccm, and an etching time is in a range from 30 seconds to 1 minute. Thereafter, an anisotropic etching is used to remove the insulating layer 235 to obtain a shape such as shown in FIG. 72.
As shown in FIG. 73, the thin capacitor insulating film 212 formed of, e.g., a silicon nitride film is formed on the surface of the capacitor lower electrode 211. As shown in FIG. 74, the cell plate 213 made of electrically conductive polysilicon is formed on the whole surface. Thereby, the cylindrical stacked type capacitor 210, which includes the base portions 211a and standing wall portions 211b forming the capacitor lower electrode 211 as well as the capacitor insulating film 212 and cell plate 213 is completed.
As shown in FIG. 75, the cell plate 213 is covered with the thick interlayer insulating film 214. The interconnection layers 215 of, e.g., aluminium having predetermined configurations are formed on the surface of the interlayer insulating film 214.
Finally, as shown in FIG. 61, the surfaces of the interconnection layers 215 are covered with the protection film 216. By the foregoing steps, the memory cells of the conventional DRAM are formed
FIG. 76 is an enlarged view showing a portion of the conventional DRAM indicated by "J" in FIG. 75. Referring to FIG. 76, the conventional DRAM described above includes the capacitor lower electrode (storage node), of which standing wall portion 211b has a sharp tip end and a rough side surface. Thus, a side surface of the standing wall portion 211b has a significantly large roughness in the range of about 250 .ANG. to about 500 .ANG.. These configurations are formed by the RIE step which has been described with reference to FIGS. 70 and 71. FIGS. 77-79 schematically show etching states in the RIE step already described with reference to FIGS. 70 and 71. Referring to FIGS. 77-79, steps for forming the standing wall portion 211b having the configuration shown in FIG. 76 will be described below.
First, as shown in FIG. 77, electrically neutral Cl radical particles 250 are chemically absorbed onto the polysilicon layer 211d in the RIE step. When accelerated CL.sup.+ ions impinge against the chemically absorbed Cl radial particles 250, the Cl radical particles 250, which obtain an energy, combines with Si to form SiCL.sub.4 and evaporates. Since this etching is anisotropic, the etching progresses mainly in the polysilicon layer 211d formed on the upper surface of the insulating layer 235. However, the etching progresses in the surface portion of the polysilicide layer 211d formed on the side surface of the insulating layer 235 to a slight extent, as shown in FIG. 78. Since the RIE (reaction ion etching) is liable to progress along a grain boundary, the surface of the polysilicon layer 211d formed on the side surface of the insulating layer 235 becomes irregular and uneven. Therefore, after the polysilicon layer 211d on the insulating layer 235 is fully etched, the standing wall portion 211b formed of the polysilicon layer 211d, which is formed on the side surface of the insulating layer 235, has the sharp tip end and the rough side surface of a roughness between 250 .ANG. and 500 .ANG..
As described above, since the standing wall portion 211b in the prior art is formed utilizing the RIE in which the etching progresses owing to the reaction of the Si and Cl, the standing wall portion 211b disadvantageously has the sharp tip end and the rough side surface. This reduces lifetime of the capacitor insulating film 212. More specifically, the electric field concentrates at the tip end of the standing wall portion 211b, so that the lifetime of the capacitor insulating film 212 reduces. The uneven shape of the side surface of the standing wall portion 211b causes an irregular electric field, which also reduces the lifetime of the insulating film.